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1 ds05-11209-1e fujitsu semiconductor data sheet memory cmos 4m 32 fast page mode dram module MB85391A-60/-70 cmos 4m 32 bit fast page mode dram module n description the fujitsu mb85391a is a fully decoded, cmos dynamic random access memory (dram) module consisting of eight mb8117400a devices. the mb85391a is optimized for those applications requiring high speed, high performance and large memory storage. the operation and electrical characteristics of the mb85391a are the same as the mb8117400a which features fast page mode operation. for ease of memory expansion, the mb85391a is offered in a 72-pad single in-line memory module package (simm). n absolute maximum ratings (see note) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit supply voltage v cc ?.5 to +7.0 v input voltage v in ?.5 to +7.0 v output voltage v out ?.5 to +7.0 v short circuit output current i out 50 ma power dissipation p d 8w storage temperature t stg ?5 to +125 c this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 MB85391A-60/mb85391a-70 n product line & features parameter MB85391A-60 mb85391a-70 ras access time 60 ns max. 70 ns max. random cycle time 110 ns min. 130 ns min. address access time 30 ns max. 35 ns max. cas access time 15 ns max. 17 ns max. fast page mode cycle time 40 ns min. 45 ns min. power dissipation operating mode 4620 mw max. 3960 mw max. standby mode 44mw(cmos) / 88mw(ttl) mss-72p-p79 2,048 refresh cycles/32.8ms package and ordering information: 72-pad simm, order as mb85391a?xpjpb (pjpb = solder pad mb85391a?xpjpbk (pjpbk = gold pad n pin assignment 67 68 69 70 pin # symbol pd1 pd2 pd3 pd4 -60 -70 v ss v ss v ss nc nc nc nc nc organization: 4,194,304 words x 32 bits memory : mb8117400a, 8 pcs decoupling capacitor, 8 pcs 5.0 v 10% supply voltage fast page operation mss-72p-p77 n package 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 dq0 dq1 dq2 dq3 vcc a0 a2 a4 a6 dq4 dq5 dq6 dq7 a7 vcc a9 ras 2 nc nc cas 0 cas 3 ras 0 nc nc dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 nc pd2 pd4 vss vss dq16 dq17 dq18 dq19 nc a1 a3 a5 a10 dq20 dq21 dq22 dq23 nc a8 nc nc nc vss cas 2 cas 1 nc we dq8 dq9 dq10 dq11 dq12 vcc dq13 dq14 dq15 pd1 pd3 nc 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
3 MB85391A-60/mb85391a-70 functional block diagram cas 0 ras 0 cas 1 cas 3 cas 2 ras 2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 a0 ?a10 v cc v ss we i/o i/o i/o i/o a0-a10 chip 00 w cas ras we i/o i/o i/o i/o a0-a10 chip 02 w cas ras we i/o i/o i/o i/o a0-a10 chip 04 w cas ras we i/o i/o i/o i/o a0-a10 chip 06 w cas ras we i/o i/o i/o i/o a0-a10 chip 01 w cas ras we i/o i/o i/o i/o a0-a10 chip 03 w cas ras we i/o i/o i/o i/o a0-a10 chip 05 w cas ras we i/o i/o i/o i/o a0-a10 chip 07 w cas ras we c0-7 chips 00?7 chips 00?7
4 MB85391A-60/mb85391a-70 n recommended operating conditions (referenced to v ss ) note: *undershoots of up to ?.0 volts with a pulse width not exceeding 10 ns are acceptable. n dc characteristics (recommended operating conditions unless otherwise noted.) notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rate. the speci? values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih , v il > ?.3 v. i cc1 , i cc3 , and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . i cc4 is specified at one time of address change during one page cycle. parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v ground v ss 000v input high voltage, all inputs v ih 2.4 6.5 v input low voltage, all inputs* v il ?.3 0.8 v ambient temperature t a 02570 c parameter symbol test condition min. max. unit output high voltage* 1 v oh i oh = ? ma 2.4 v output low voltage* 1 v ol i ol = 4.2 ma 0.4 v input leakage current ras 0, ras 2 i i (l) 0 v v in 5.5 v, 4.5 v v cc 5.5 v, v ss = 0 v, all other pins under test = 0 v ?0 30 m a cas 0 ?cas 3 ?0 20 address, we ?0 60 output leakage current i o( l ) 0 v v out 5.5 v, 4.5 v v cc 5.5 v, data out disabled ?0 10 m a operating current* 2 (average power supply current) MB85391A-60 i cc1 ras & cas cycling, t rc = min. 840 ma mb85391a-70 720 standby current* 2 (power supply current) ttl level i cc2 ras = cas =v ih ?6 ma cmos level ras = cas 3 v cc ?.2 v 8 refresh current #1* 2 (average power supply current) MB85391A-60 i cc3 cas = v ih , ras = cycling, t rc = min. 840 ma mb85391a-70 720 fast page mode current* 2 MB85391A-60 i cc4 ras = v il , cas = cycling, t pc = min. 560 ma mb85391a-70 520 refresh current #2* 2 (average power supply current) MB85391A-60 i cc5 ras = cycling, cas -before- ras , t rc = min. 840 ma mb85391a-70 720
5 MB85391A-60/mb85391a-70 n ac characteristics (recommended operating conditions unless otherwise noted.) notes 1, 2, 3 (continued) no. parameter symbol MB85391A-60 mb85391a-70 unit notes min. max. min. max. 1 time between refresh t ref 32.8 32.8 ms 2 random read/write cycle time t rc 110 130 ns 3 access time from ras t rac ?0?0ns4, 7 4 access time from cas t cac ?5?7ns5, 7 5 column address access time t aa ?0?5ns6, 7 6 output hold time t oh 3?ns 7 output buffer turn on delay time t on 0?ns 8 output buffer turn off delay time t off ?5?7ns8 9 transition time t t 350350ns 10 ras precharge time t rp 40?0ns 11 ras pulse width t ras 60 100000 70 100000 ns 12 ras hold time t rsh 15?7ns 13 cas to ras precharge time t crp 0?ns 14 ras to cas delay time t rcd 20 45 20 53 ns 9, 10 15 cas pulse width t cas 15 10000 17 10000 ns 16 cas hold time t csh 60?0ns 17 cas precharge time (c-b-r refresh) t cpn 10?0ns17 18 row address setup time t asr 0?ns 19 row address hold time t rah 10?0ns 20 column address setup time t asc 0?ns 21 column address hold time t cah 15?5ns 22 column address hold time from ras t ar 35?5ns 23 ras to column address delay time t rad 15 30 15 35 ns 11 24 column address to ras lead time t ral 30?5ns 25 column address to cas lead time t cal 30?5ns 26 read command setup time t rcs 0?ns 27 read command hold time referenced to ras t rrh 0?ns12 28 read command hold time referenced to cas t rch 0?ns12 29 write command setup time t wcs 0?ns13 30 write command hold time t wch 15?5ns
6 MB85391A-60/mb85391a-70 n ac characteristics (continued) (recommended operating conditions unless otherwise noted.) notes 1, 2, 3 no. parameter symbol MB85391A-60 mb85391a-70 unit notes min. max. min. max. 31 write command hold time from ras t wcr 35 35 ns 32 we pulse width t wp 15 15 ns 33 write command to ras lead time t rwl 15 17 ns 34 write command to cas lead time t cwl 15 17 ns 35 din setup time t ds 0?ns 36 din hold time t dh 15 15 ns 37 data hold time from ras t dhr 35 35 ns 38 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 39 cas setup time (c-b-r refresh) t csr 0?ns 40 cas hold time (c-b-r refresh) t chr 10 12 ns 41 we setup time from ras t wsr 0 0 ns 18 42 we hold time from ras t whr 10 10 ns 18 43 din to cas delay time t dzc 0 0 ns 15 44 fast page mode cas pulse width t rasp 100000 100000 ns 45 fast page mode read/write cycle time t pc 40 45 ns 46 access time from cas precharge t cpa 35 40 ns 7, 16 47 fast page mode cas precharge time t cp 10 10 ns 48 fast page mode ras hold time from cas precharge t rhcp 35 40 ns
7 MB85391A-60/mb85391a-70 notes: 1. an initial pause (ras = cas =v ih ) of 200 m s is required after power-up followed by any eight ras -only cycles before proper device operation is achieved. if an internal refresh counter is used, a minimum of eight cas -before-ras initialization cycles are required instead of eight ras cycles. 2. ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring the timing of input signals. transition times are measured between v ih (min.) and v il (max.). 4. assumes that t rcd t rcd (max.), t rad t rad (max.). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. 5. if t rcd 3 t rcd (max.), t rad 3 t rad (max.), and t asc 3 t aa ?t cac ?t t , access time is t cac . 6. if t rad 3 t rad (max.) and t asc t aa ?t cac ?t t , access time is t aa . 7. measured with a load equivalent to two ttl loads and 100 pf. 8. t off is speci?d that output buffer change to high impedance state. 9. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max.) limit, access time is controlled exclusively by t cac or t aa . 10. t rcd (min.) = t rah (min.)+ 2 t t + t asc (min.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max.) limit, access time is controlled exclusively by t cac or t aa . 12. either t rrh or t rch must be satis?d for a read cycle. 13. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min.) the data output pin will remain high-z state through entire cycle. 14. assumes that t wcs < t wcs (min.). 15. either t dzc or t dzo must be satis?d. 16. t cpa is access time from the selection of a new column address (caused by changing cas from ? to ??. therefore, if t cp become long, t cpa also become longer than t cpa (max.). 17. assumes that cas -before-ras refresh. 18. assumes that test mode function. *source: see mb8117400a data sheet for details on the electricals.
8 MB85391A-60/mb85391a-70 n capacitance (t a = 25 c, f = 1 mhz) parameter symbol min. max. unit input capacitance, a0 to a10 c in1 ?1pf input capacitance, ras 0 and ras 2c in2 ?9pf input capacitance, cas 0 to cas 3c in3 ?3pf input capacitance, we c in4 ?6pf i/o capacitance, (dq0-dq31) c dq ?2pf
9 MB85391A-60/mb85391a-70 n package dimensions (suf?: pjpbk) .080 .005 (2.03 0.13) r .062 .002 (r 1.57 0.05) 3.984 .004 (101.19 0.10) 4.250 .005 (107.95 0.13) .225 min (5.72 min) ?.125 .002 (?3.18 0.05) .400 .003 (10.16 0.08) r .062 .002 (r 1.57 0.05) 72-pad plastic single in-line type module (case no.: mss-72p-p77) ? 1995 fujitsu limited m72071sc-1 dimensions in inches (millimeters) .041(1.04) typ .010(0.25) max .250 .005 (6.35 0.13) detail +.004 ?003 +0.10 ?.08 .050 .001 (1.27 0.03) .250 .001 (6.35 0.03) .250 .005 (6.35 0.13) .200 max (5.08 max) 3.750 .002 (95.25 0.05) .995 .005 (25.27 0.13) detail .100(2.54) min 1.750 .002 (44.45 0.05) resistor mounting area 1 pin no.1 index .050 (1.27 )
10 MB85391A-60/mb85391a-70 n package dimensions (suf?: pjpb) 72-pad plastic single in-line type module (case no.: mss-72p-p79) ? 1995 fujitsu limited m72071sc-1 dimensions in inches (millimeters) .041(1.04) typ .010(0.25) max .250 .005 (6.35 0.13) r .062 .002 (r 1.57 0.05) detail .050 +.006 ?003 (1.27 ) +0.15 ?.08 .050 .001 (1.27 0.03) .080 .005 (2.03 0.13) .250 .001 (6.35 0.03) 3.750 .002 (95.25 0.05) .400 .003 (10.16 0.08) 3.984 .004 (101.19 0.10) .995 .005 (25.27 0.13) 4.250 .005 (107.95 0.13) detail .100(2.54) min 1.750 .002 (44.45 0.05) resistor mounting area r .062 .002 (r 1.57 0.05) 1 ?125 .002 (?3.18 0.05) .250 .005 (6.35 0.13) pin no.1 index .200 max (5.08 max) .225 min (5.72 min)
11 MB85391A-60/mb85391a-70 all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9704 ? fujitsu limited printed in japan

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